- author = "Michael Tetteh and Douglas Mota Dias and Conor Ryan",
- title = "Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with {SystemVerilog}",
- booktitle = "EuroGP 2021: Proceedings of the 24th European Conference on Genetic Programming",
- year = "2021",
- editor = "Ting Hu and Nuno Lourenco and Eric Medvet",
- series = "LNCS",
- volume = "12691",
- publisher = "Springer Verlag",
- address = "Virtual Event",
- pages = "146--161",
- month = "7-9 " # apr,
- organisation = "EvoStar, Species",
- keywords = "genetic algorithms, genetic programming, Grammatical Evolution, Digital circuit design, Evolvable Hardware, EHW, Hardware Description Languages, HDLs, Verilog, System Verilog, Yosys",
- isbn13 = "978-3-030-72811-3",
-
DOI = "
doi:10.1007/978-3-030-72812-0_10",
- abstract = "Scalability problems have hindered the progress of Evolvable Hardware in tackling complex circuits. The two key issues are the amount of testing (for example, a 64-bit x 64-bit add-shift multiplier problem has 264+64 test cases) and low level that hardware works at: a circuit to implement 64-bit by 64-bit add-shift multiplier would require approximately 33234 gates when synthesized using the powerful Yosys Open SYnthesis Suite tool. We use Grammatical Evolution and SystemVerilog, a Hardware Description Language (HDL), to evolve fully functional parameterised adder, multiplier and selective parity circuits with default input bit-width sizes of 64-bit + 64-bit, 64-bit by 64-bit and 128-bit respectively...",
-
notes = "Lero BDS. Corner cases. Lexicase selection.
Parameterised for loop in BNF grammar. Always block in
BNF grammar.
http://www.evostar.org/2021/eurogp/ Part of \cite{Hu:2021:GP} EuroGP'2021 held in conjunction with EvoCOP2021, EvoMusArt2021 and EvoApplications2021",
