Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with SystemVerilog

Abstract

Scalability problems have hindered the progress of Evolvable Hardware in tackling complex circuits. The two key issues are the amount of testing (for example, a 64-bit $\times$ 64-bit add-shift multiplier problem has $2^{64 + 64}$ test cases) and low level that hardware works at: a circuit to implement 64-bit $\times$ 64-bit add-shift multiplier would require approximately 33,234 gates when synthesized using the powerful Yosys Open SYnthesis Suite tool. We use Grammatical Evolution and SystemVerilog, a Hardware Description Language (HDL), to evolve fully functional parameterized adder, multiplier and selective parity circuits with default input bit-width sizes of 64-bit + 64-bit, 64-bit $\times$ 64-bit and 128-bit respectively.

These are substantially larger than the current state of the art for evolutionary approaches, specifically, 6.4$\times$ (adder), 10.7$\times$ (multiplier), and 6.7$\times$ (parity). We are able to scale so dramatically because our use of an HDL permits us to operate at a far higher level of abstraction than most other approaches. This has the additional benefit that no further evolutionary experiments are needed to design different input bit-width sizes of the same circuit as is the case for existing EHW approaches. Thus, one can evolve once and reuse multiple times, simply by specifying the newly desired input/output bit-width sizes during module instantiation.

For example, 32-bit $\times$ 32-bit and 256-bit $\times$ 256-bit multipliers can be instantiated from an evolved parameterized multiplier. We also adopt a method for reducing testing from Digital Circuit Design known as corner case testing, well-known technique heavily relied upon by circuit designers to avoid time-consuming exhaustive testing; we demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits with a huge number of inputs.

We obtain successful results (ranging from 72% to 100%) on each benchmark and all three problems were tackled without resorting to the use of any standard decomposition methods due to our ability to use high-level programming constructs and operators available in SystemVerilog.

The authors are supported by Research Grant 16/IA/4605 from the Science Foundation Ireland and by Lero, the Irish Software Engineering Research Centre. The second author is partially financed by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001.

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