- author = "Fabian Ritter",
- title = "Inferring and Analyzing Microarchitectural Performance Models",
- school = "Fakultaet fuer Mathematik und Informatik der Universitaet des Saarlandes",
- year = "2024",
- address = "Germany",
- month = "9 " # oct,
- keywords = "genetic algorithms, genetic programming, EHW, PMEvo, AMD, SMT",
-
URL = "
https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/38955/1/ritter-dissertation.pdf",
- size = "230 pages",
-
abstract = "Modern processors are complex systems that employ a
wide range of techniques to execute programs as fast
and efficiently as possible. However, these hardware
intricacies make reasoning about the efficiency of code
for the processor difficult. Microarchitectural
performance models are therefore indispensable for
estimating and improving how efficiently software takes
advantage of the hardware. This dissertation presents
several advancements in the field of microarchitectural
performance modeling.
The first part of this thesis proposes techniques to characterize how a processor exploits instruction-level parallelism. Based on a formal model, we explore ways to infer a processor’s port mapping from throughput measurements, i.e., how it splits instructions into micro-operations and how these are executed on the processor’s functional units. Our techniques enable accurate port mapping inference for processors that prior methods could not reason about.
In the second part, we introduce AnICA, a method to analyze inconsistencies between performance models. AnICA takes inspiration from differential testing and abstract interpretation to systematically characterize differences in the outputs of basic block throughput predictors. It can summarize thousands of inconsistencies in a few dozen descriptions that provide high-level insights into the differing behaviors of such predictors. These results have lead to improvements in the scheduling models of the widely used LLVM compiler infrastructure.",
-
notes = "Is this GP? 'In Chapter 5, we use an evolutionary
algorithm to find port mappings that explain observed
throughputs'
Supervisor: Sebastian Hack",
