Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware
Created by W.Langdon from
gp-bibliography.bib Revision:1.7970
- @Article{Vasicek:2011:GPEM,
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author = "Zdenek Vasicek and Lukas Sekanina",
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title = "Formal verification of candidate solutions for
post-synthesis evolutionary optimization in evolvable
hardware",
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journal = "Genetic Programming and Evolvable Machines",
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year = "2011",
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volume = "12",
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number = "3",
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pages = "305--327",
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month = sep,
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note = "Special Issue Title: Evolvable Hardware Challenges",
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keywords = "genetic algorithms, genetic programming, Cartesian
Genetic Programming",
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ISSN = "1389-2576",
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DOI = "doi:10.1007/s10710-011-9132-7",
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size = "23 pages",
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abstract = "We use a formal verification algorithm to reduce the
fitness evaluation time for evolutionary post-synthesis
optimisation in evolvable hardware. The proposed method
assumes that a fully functional digital circuit is
available. A post-synthesis optimisation is then
conducted using Cartesian Genetic Programming (CGP)
which uses a satisfiability problem solver to decide
whether a candidate solution is functionally correct or
not. It is demonstrated that the method can optimise
digital circuits of tens of inputs and thousands of
gates. Furthermore, the number of gates was reduced for
the LGSynth93 benchmark circuits by 37.8percent on
average with respect to results of the conventional SIS
tool.",
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notes = "Silver winner 2011 HUMIES GECCO 2011
",
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affiliation = "Faculty of Information Technology, Brno University of
Technology, Brno, Czech Republic",
- }
Genetic Programming entries for
Zdenek Vasicek
Lukas Sekanina
Citations