A SAT-based fitness function for evolutionary optimization of polymorphic circuits
Created by W.Langdon from
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- @InProceedings{Sekanina:2012:DATE2,
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author = "Lukas Sekanina and Zdenek Vasicek",
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title = "A SAT-based fitness function for evolutionary
optimization of polymorphic circuits",
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booktitle = "Design, Automation Test in Europe Conference
Exhibition (DATE), 2012",
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year = "2012",
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month = "12-16 " # mar,
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pages = "715--720",
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size = "6 pages",
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abstract = "Multifunctional (or polymorphic) gates have been used
as building blocks for multifunctional circuits that
are capable of performing various logic functions under
different settings of control signals. In order to
effectively synthesise polymorphic circuits, several
methods have been developed in the recent years.
Unfortunately, the methods are applicable for small
circuits only. In this paper, we propose a SAT-based
functional equivalence checking algorithm to eliminate
the fitness evaluation time which is the most critical
overhead for genetic programming-based design and
optimisation of complex polymorphic circuits. The
proposed approach has led to a 20percent-40percent
reduction in gate count with respect to the solutions
created using the polymorphic multiplexing.",
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keywords = "genetic algorithms, genetic programming, SAT-based
fitness function, SAT-based functional equivalence
checking algorithm, complex polymorphic circuit
optimisation, evolutionary optimisation, genetic
programming-based design, logic function,
multifunctional circuit, multifunctional gate,
polymorphic circuit synthesis, polymorphic gate,
polymorphic multiplexing, circuit optimisation,
computability, logic gates",
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URL = "http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6176563",
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DOI = "doi:10.1109/DATE.2012.6176563",
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ISSN = "1530-1591",
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notes = "Also known as \cite{6176563}",
- }
Genetic Programming entries for
Lukas Sekanina
Zdenek Vasicek
Citations