CGP Acceleration Using Field-Programmable Gate Arrays
Created by W.Langdon from
gp-bibliography.bib Revision:1.7954
- @InCollection{Sekanina:2011:CGP.ch7,
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author = "Lukas Sekanina and Zdenek Vasicek",
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title = "CGP Acceleration Using Field-Programmable Gate
Arrays",
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booktitle = "Cartesian Genetic Programming",
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publisher = "Springer",
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editor = "Julian F. Miller",
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year = "2011",
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series = "Natural Computing Series",
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chapter = "7",
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pages = "217--230",
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keywords = "genetic algorithms, genetic programming, Cartesian
Genetic Programming",
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isbn13 = "978-3-642-17309-7",
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URL = "http://www.springer.com/computer/theoretical+computer+science/book/978-3-642-17309-7",
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DOI = "doi:10.1007/978-3-642-17310-3_7",
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abstract = "In Chapter 5 we described an application specific
integrated circuit consisting of programmable
polymorphic nodes that resembled the CGP
representation. A search algorithm, running on an
external personal computer, was used to evolve
configurations as well as interconnection of the nodes.
In this chapter we describe how complete CGP system
(i.e., the array of programmable nodes and search
algorithm) can be implemented on a single chip. The
implementation is carried out using a
field-programmable gate array (FPGA) a reconfigurable
chip which provides a high performance and flexibility
in computing for a moderate cost. In comparison with
CGP running on a personal computer, the main advantages
of the FPGA implementation are a significant speed-up
that can be obtained for many applications and a
possibility to build small low-power adaptive embedded
systems. This chapter introduces the complete FPGA
implementations of CGP which can typically be used to
accelerate combinational circuit evolution (see Chapter
5) and image filter evolution (see Chapter 6).",
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notes = "part of \cite{Miller:CGP}",
- }
Genetic Programming entries for
Lukas Sekanina
Zdenek Vasicek
Citations