Evolutionary circuit design for fast FPGA-based classification of network application protocols
Created by W.Langdon from
gp-bibliography.bib Revision:1.7970
- @Article{Grochol:2016:ASC,
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author = "D. Grochol and L. Sekanina and M. Zadnik and
J. Korenek and V. Kosar",
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title = "Evolutionary circuit design for fast FPGA-based
classification of network application protocols",
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journal = "Applied Soft Computing",
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volume = "38",
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pages = "933--941",
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year = "2016",
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ISSN = "1568-4946",
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DOI = "doi:10.1016/j.asoc.2015.09.046",
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URL = "http://www.sciencedirect.com/science/article/pii/S1568494615006262",
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abstract = "The evolutionary design can produce fast and efficient
implementations of digital circuits. It is shown in
this paper how evolved circuits, optimized for the
latency and area, can increase the throughput of a
manually designed classifier of application protocols.
The classifier is intended for high speed networks
operating at 100 Gbps. Because a very low latency is
the main design constraint, the classifier is
constructed as a combinational circuit in a field
programmable gate array (FPGA). The classification is
performed using the first packet carrying the
application payload. The improvements in latency (and
area) obtained by Cartesian genetic programming are
validated using a professional FPGA design tool. The
quality of classification is evaluated by means of real
network data. All results are compared with commonly
used classifiers based on regular expressions
describing application protocols.",
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keywords = "genetic algorithms, genetic programming, Application
protocol, Classifier, Field programmable gate array",
- }
Genetic Programming entries for
David Grochol
Lukas Sekanina
Martin Zadnik
Jan Korenek
V Kosar
Citations