Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming
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- @InProceedings{Gajda:2009:cec,
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author = "Zbysek Gajda and Lukas Sekanina",
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title = "Gate-Level Optimization of Polymorphic Circuits Using
Cartesian Genetic Programming",
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booktitle = "2009 IEEE Congress on Evolutionary Computation",
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year = "2009",
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editor = "Andy Tyrrell",
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pages = "1599--1604",
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address = "Trondheim, Norway",
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month = "18-21 " # may,
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organization = "IEEE Computational Intelligence Society",
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publisher = "IEEE Press",
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isbn13 = "978-1-4244-2959-2",
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file = "P186.pdf",
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DOI = "doi:10.1109/CEC.2009.4983133",
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abstract = "Polymorphic digital circuits contain ordinary and
polymorphic gates. In the past, Cartesian Genetic
Programming (CGP) has been applied to synthesize
polymorphic circuits at the gate level. However, this
approach is not scalable. Experimental results
presented in this paper indicate that larger and more
efficient polymorphic circuits can be designed by a
combination of conventional design methods (such as
BDD, Espresso or ABC System) and evolutionary
optimization (conducted by CGP). Proposed methods are
evaluated on two benchmark circuits - Multiplier/Sorter
and Parity/Majority circuits of variable input size.",
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keywords = "genetic algorithms, genetic programming, cartesian
genetic programming",
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notes = "CEC 2009 - A joint meeting of the IEEE, the EPS and
the IET. IEEE Catalog Number: CFP09ICE-CDR",
- }
Genetic Programming entries for
Zbysek Gajda
Lukas Sekanina
Citations