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A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C

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Abstract

This paper presents an implementation of Genetic Programming using a Field Programmable Gate Array. This novel implementation uses a high level language to hardware compilation system, called Handel-C, to produce a Field Programmable Logic Array capable of performing all the functions required of a Genetic Programming System. Two simple test problems demonstrate that GP running on a Field Programmable Gate Array can outperform a software version of the same algorithm by exploiting the intrinsic parallelism available using hardware, and the geometric parallelisation of Genetic Programming.

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References

  1. D. Andre and J. R. Koza. “Parallel genetic programming: A scalable implementation using the transputer network architecture,” in Advances in Genetic Programming 2, P. J. Angeline and K. E. Kinnear, Jr. (eds.), MIT Press: Cambridge, MA, 1996, chap. 16, pp. 317-338.

    Google Scholar 

  2. W. Banzhaf P. Nordin R. E. Keller, and F. D. Francome, Genetic Programming-An Introduction; On the Automatic Evolution of Computer Programs and its Applications, Morgan Kaufmann: Los Altos, CA, 1998.

    Google Scholar 

  3. E. Cantu-Paz, “A survey of parallel genetic algorithms,” Calculateurs Parallels, Reseaux et Systems Repartis, vol. 10(2), pp. 141-171, 1998.

    Google Scholar 

  4. Celoxica, Handel-C Language Reference Manual, Celoxica Ltd., 20 Park Gate, Milton Park, Abingdon, Oxfordshire, OX14 4SH, UK, 2.1 edition, 2001. Vendors of Handel-C.

    Google Scholar 

  5. Celoxica, Web site of Celoxica Ltd, www.celoxica.com, 2001, Vendors of Handel-C. Last visited 15/June/2001.

  6. F. S. Chong and W. B. Langdon, “Java based distributed genetic programming on the internet,” in Proc. Genetic and Evolutionary Comput. Conf., Orlando, FL, W. Banzhaf J. Daida A. E. Eiben M. H. Garzon V. Honavar M. Jakiela, and R. E. Smith (eds.), vol. 2, Morgan Kaufmann: Los Altos, CA, 13-17 July, 1999, pp. 1229.

    Google Scholar 

  7. T. Fogarty J. Miller, and P. Thompson, “Evolving digital logic circuits on Xilinx 6000 family FPGAs,” in Soft Computing in Engineering Design and Manufacturing, P. Chawdhry R. Roy, and R. Pant (eds.), Springer: Berlin, 1998, pp. 299-305.

    Google Scholar 

  8. P. Graham and B. Nelson, “Genetic algorithms in software and in hardware-A performance analysis of workstation and custom computing machine implementations,” in Proc. Fourth IEEE Symp. FPGAs for Custom Comput. Mach., K. Pocek and J. Arnold (eds.), IEEE Computer Society Press: Napa Valey, CA, Apr., 1996, pp. 216-225.

    Google Scholar 

  9. M. I. Heywood and A. N. Zincir-Heywood, “Register based genetic programming on FPGA computing platforms,” in Genetic Programming, Proc. EuroGP' 2000, R. Poli W. Banzhaf W. B. Langdon J. F. Miller P. Nordin, and T. C. Fogarty (eds.), LNCS, vol. 1802, Edinburgh, Springer: Berlin, 15-16 Apr., 2000, pp. 44-59.

    Google Scholar 

  10. E. Knuth, Donald, Semi Numerical Algorithms, Addison-Wesley: Reading, MA, 1969, vol. 2.

    Google Scholar 

  11. J. R. Koza, Genetic Programming: On the Programming of Computers by Means of Natural Selection, MIT Press: Cambridge, MA, 1992.

    Google Scholar 

  12. J. R. Koza F. H. Bennett III J. L. Hutchings S. L. Bade M. A. Keane, and D. Andre, “Evolving sotring networks using genetic programming and the rapidly reconfigurable xilinx 6216 fieldprogrammable gate array,” in Proc. 31st Asilomar Conf. Signals, Systems, and Comp., IEEE Press: NewY ork, 1997.

    Google Scholar 

  13. J. R. Koza M. A. Keane J. Yu F. H. Bennett III, and W. Mydlowec, “Evolution of a controller with a free variable using genetic programming,” in Genetic Programming, Proc. EuroGP' 2000, R. Poli W. Banzhaf W. B. Langdon J. F. Miller P. Nordin, and T. C. Fogarty (eds.), LNCS, vol. 1802, Edinburg, Springer: Berlin, 15-16 Apr., 2000, pp. 91-105.

    Google Scholar 

  14. D. Levi and S. Guccione, “Genetic FPGA: evolving stable circuits on mainstream FPGA devices,” in Proc. First NASA/DoD Workshop on Evolvable Hardware, A. Stoica D. Keymeulen, and J. Lohn (eds.), IEEE Computer Society: Silver Spring, MD, July 1999, pp. 12-17.

    Google Scholar 

  15. G. Marsaglia, Web site for Diehard random number test suite, http://stat.fsu.edu/geo/, 2001. Last visited 15/June/2001.

  16. M. Meissner, Web site for Power-pc simulator-psim. http://sources.redhat.com/psim/, 2001. Last visited 15/June/2001.

  17. Motorola, PowerQuicc MPC860 User's Manual, Motorola Inc., Motorola Literature Distribution, P. O. Box 5405, Denver, CO 80217, rev. 1 edition, 1998.

    Google Scholar 

  18. P. Nordin and W. Banzhaf, “Evolving turning-complete programs for a register machine with selfmodifying code,” in Genetic Algorithms: Proc. Sixth Int. Conf. (ICGA95), L. Eshelman (ed.), Pittsburgh, PA. Morgan Kaufmann: Los Altos, CA, 15-19 July 1995, pp. 318-325.

    Google Scholar 

  19. M. Nowostawski and R. Poli, “Parallel genetic algorithm taxonomy,” in Proc. Third Int. Conf. Knowledge-Based Intell. Inf. Engrg. Syst. KES'99, IEEE Computer Society: New York, Aug. 1999, pp. 88-92.

    Google Scholar 

  20. I. Page, “Constructing hardware-software systems from a single description,” J. VLSI Signal Proc., vol. 1(12), pp. 87-107, 1996.

    Google Scholar 

  21. I. Page, “Compiling video algorithms into hardware,” Embedded System Engineering, Sept. 1997.

  22. S. Perkins R. Porter, and N. Harvey, “Everything on the chip: A hardware-based self-contained spatially-structured genetic algorithm for signal processing,” in Proc. 3rd Int. Conf. Evolvable Syst.: From Biology to Hardware (ICES 2000), J. Miller A. Thompson P. Thompson, and T. Fogarty (eds.), Lecture Notes in Computer Science, vol. 1801, Edinburg, UK, Springer: Berlin, 2000, pp. 165-174.

    Google Scholar 

  23. B. Schneier, Applied Cryptography. Protocols, Algorithms, and Source Code in C, Wiley: NewYork, 1996.

    Google Scholar 

  24. D. Scott S. Seth, and A. Samal, “A hardware engine for genetic algorithms,” Technical Report uUNL-CSE-97-001, Dept. Computer Science and Engineering, University of Nebraska-Lincon, 4 July, 1997.

  25. R. Sedgewick, Algorithms, Addison-Wesley: Reading, MA, 1984.

    Google Scholar 

  26. B. Shackleford G. Snider R. Carter E. Okushi M. Yasuda K. Seo, and H. Yasuura, “A high performance, pipelined, FPGA-based genetic algorithm machine,” Genetic Programming and Evolvable Machines, vol. 2(1), pp. 33-60, 2001.

    Google Scholar 

  27. D. Sulik M. Vasilko D. Durackova, and P. Fuchs, “Design of a RISC microcontroller core in 48 hours. Unpublished paper, Bournemouth University, May 2000. http://dec.bournemouth.ac.uk/drhw/-publications/sulik-risc48hrs.pdf Embedded Systems Show2000, London Olympia, UK.

  28. A. Thompson, “Silicon evolution,” in Genetic Programming 1996: Proc. First Ann. Conf., J. R. Koza D. E. Goldberg D. B. Fogel, and R. L. Riolo, (eds.), Stanford University, CA, MIT Press: Cambridge, MA, 28-31 July 1996, pp. 444-452.

    Google Scholar 

  29. A. Thompson and P. Layzell, “Analysis of unconventional evolved electronics,” Commun. ACM, 42(4), pp. 71-79, 1999.

    Google Scholar 

  30. G. Tufte and P. Haddow, “Prototyping a GA pipeline for complete hardware evolution,” in Proc. First NASA/DoD Workshop on Evolvable Hardware, A. Stoica D. Keymeulen, and J. Lohn (eds.), IEEE Computer Society: NewY ork, July 1999, pp. 18-25.

    Google Scholar 

  31. Xilinx, Web site of Xilinx for FPGA data sheets, www.xilinx.com, 2001. Last visited 15/June/2001.

  32. Y. Yamaguchi A. Miyashita T. Marutama, and T. Hoshino, “A co-processor system with a virtex FPGA for evolutionary computations,” in 10th Int. Conf. Field Programmable Logic Appl. (FPL 2000), R. Hartenstein and H. Grunbacher (eds.), Lecture Notes in Computer Science, vol. 1896, Springer: Berlin, Aug. 2000, pp. 240-249.

    Google Scholar 

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  1. School of Computer Science, The University of Birmingham, Birmingham, B15 2TT, UK

    Peter Martin

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Martin, P. A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C. Genetic Programming and Evolvable Machines 2, 317–343 (2001). https://doi.org/10.1023/A:1012942304464

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