On the feasibility of using evolvable hardware for hardware Trojan detection and prevention

Highlights

• We are the first to investigate the use of EH for HTH detection and prevention.

• We implement a VRC as a virtual overlay architecture on an FPGA for preventing HTHs.

• We compare two approaches for the generation of new configurations (GP and CGP).

• We evaluate the overhead of the VRC architecture on an FPGA resources.

• We discuss the limitations of the proposed solution and the application scenarios.

Abstract

Evolvable hardware (EH) architectures are capable of changing their configuration and behavior dynamically based on inputs from the environment. In this paper, we investigate the feasibility of using EH to prevent Hardware Trojan Horses (HTHs) from being inserted, activated, or propagated in a digital electronic chip. HTHs are malicious hardware components that intend to leak secret information or cause malfunctioning at run-time in the chip in which they are integrated. We hypothesize that EH can detect internal circuit errors at run-time and reconfigure to a state in which the errors are no longer present. We implement a Virtual Reconfigurable Circuit (VRC) on a Field-Programmable Gate Array (FPGA) that autonomously and periodically reconfigures itself based on an Evolutionary Algorithm (EA). New VRC configurations are generated with an on-chip EA engine.

We show that the presented approach is applicable in a scenario in which (1) the HTH-critical areas in the circuit are known in advance, and (2) the VRC is a purely combinatorial circuit, as opposed to the on-chip memory holding the golden reference, which requires one or more cycles to be read/written. We compare two different approaches for protecting the system against HTHs: Genetic Programming (GP) and Cartesian Genetic Programming (CGP). The paper reports on experiments on four benchmark circuits and gives an overview of both the limitations and the added value of the presented approaches.

Introduction

With the rise of the Internet of Things (IoT), electronic chips or integrated circuits (ICs) play an increasingly important role in our society. Often, ICs process sensitive personal or company-critical information. Nevertheless, several steps in the development of ICs are outsourced to different (sometimes untrusted) parties. This opens the door for the manipulation of ICs to extract secret information, e.g., through wireless communication or disabling (parts of) the chip. A malicious building block that is inserted in an IC to cause this undesired behavior is called a Hardware Trojan Horse (HTH).

The potential threat of HTHs was first reported by the US Department of Defense in 2005 [1]. They expressed their concerns on ICs in military applications, mainly related to untrusted foundries and untrusted actors in the supply chain. Although there are no HTHs in ICs reported in real-world applications yet, there are many examples of academic research results, both on injecting and detecting/preventing HTHs. Moreover, there was recently the alarming disclosure of a tiny chip that was added to the motherboard of servers of the company Elemental Technologies [2]. The chip that was not part of the original design of the motherboard creates a secret connection to each network in which the server is included. The fact that Elemental’s servers are massively deployed in US Defense data centers underlines the severity of the matter. Investigations showed that the chips were inserted by Chinese subcontractors during the manufacturing process.

In this paper, we investigate the possibility of using run-time reconfigurable circuits to prevent the insertion, the activation, and the propagation of HTHs. More specifically, we explore solutions based on evolvable hardware (EH) architectures, which are reconfigurable circuits that adapt their behavior dynamically through interactions with the environment. EH concentrates on the generation of efficient electronic circuits through the use of Evolutionary Algorithms (EAs). Originally, EH techniques were proposed for the efficient design of new circuits, i.e., to do a fast exploration of potential circuits with a given functionality at design-time [3]. In this case, the terms “evolutionary circuit design” and “evolved hardware” are also commonly used. Here, we consider the scenario in which the generation of new circuits is done at run-time, adapting to changes in the environment, as proposed in [4] for run-time filter updates in image processing applications.

A popular way of implementing EH architectures is through a Virtual Reconfigurable Circuit (VRC) [5]. This is a circuit that consists of programmable elements with a programmable interconnect. As opposed to commercially available configurable hardware platforms or Field-Programmable Gate Arrays (FPGAs), VRCs can be reconfigured in only one or a few clock cycles based on the direct output of an EA.

The contributions of this paper can be summarized as follows:

• We are the first to investigate the use of EH for HTH detection and prevention.

• We implement a VRC as a virtual overlay architecture on an FPGA for preventing HTH insertion, activation, and propagation.

• We compare two approaches for the generation of new configurations. The first is based on a tree structure using Genetic Programming (GP), while the second one is based on a graph structure using Cartesian Genetic Programming (CGP).

• We evaluate the overhead in FPGA resources, power consumption, and computational delay for four commonly used hardware circuits, implemented on the VRC architecture.

• We discuss the limitations of the proposed solution and the application scenarios in which the presented architectures are of interest.

The paper is structured as follows. Section 2 gives the necessary background information on HTHs in digital circuits, evolvable hardware, and VRCs. Section 3 discusses related work on HTH detection and prevention. In Section 4, we propose an FPGA architecture consisting of a VRC and an on-chip EA engine. In Section 5, we evaluate the feasibility of our approach based on four benchmark circuits. Section 6 concludes the paper and gives an outlook on future work.