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Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure

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Abstract

This study focuses on the use of genetic programming to automate the design of robust analog circuits. We define two complementary types of failure modes: partial short-circuit and partial disconnect, and demonstrated novel circuits that are resilient across a spectrum of fault levels. In particular, we focus on designs that are uniformly robust, and unlike designs based on redundancy, do not have any single point of failure. We also explore the complementary problem of designing tamper-proof circuits that are highly sensitive to any change or variation in their operating conditions. We find that the number of components remains similar both for robust and standard circuits, suggesting that the robustness does not necessarily come at significant increased circuit complexity. A number of fitness criteria, including surrogate models and co-evolution were used to accelerate the evolutionary process. A variety of circuit types were tested, and the practicality of the generated solutions was verified by physically constructing the circuits and testing their physical robustness.

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Notes

  1. The source and load resistors in the embryonic circuit are 1-K and the incoming 2 V signal is divided in half. From this, it is possible to assume that the optimal output response in low frequency area (f < 1 kHz) is 1 V. If their values are changing from damage, the optimal output response has to be changed. This results in the change of the filter’s original specification. We assume that the two resistors are tamper-proofed. Also the change of the input voltage source is not considered.

  2. The degradation ratio is defined as Current degradation / Maximum degradation.

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Acknowledgments

This work was supported in part by US National Science Foundation (NSF) CAREER grant number DMI 0547376. Co-author K.-J.K. was supported by the Korea Research Foundation Grant (KRF-2007-357-D00220) funded by the Korean Government (MOEHRD) and Korea Health 21 R&D Project, Ministry for Health, Welfare and Family Affairs (A040163).

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Author notes

  1. Kyung-Joong Kim

    Present address: Department of Computer Engineering, Sejong University, 98 Gunja-Dong, Gwangjin-Gu, Seoul, 143-747, Republic of Korea

  2. Adrian Wong

    Present address: Sandia National Laboratories, Livermore, CA, 94550, USA

Authors and Affiliations

  1. Mechanical and Aerospace Engineering, Cornell University, Ithaca, NY, 14853, USA

    Kyung-Joong Kim

  2. Electrical and Computer Engineering, Cornell University, Ithaca, NY, 14853, USA

    Adrian Wong

  3. Computing and Information Science, Cornell University, 216 Upson Hall, Ithaca, NY, 14853-7501, USA

    Hod Lipson

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  1. Kyung-Joong Kim
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  2. Adrian Wong
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Correspondence to Hod Lipson.

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Kim, KJ., Wong, A. & Lipson, H. Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure. Genet Program Evolvable Mach 11, 35–59 (2010). https://doi.org/10.1007/s10710-009-9085-2

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  • DOI: https://doi.org/10.1007/s10710-009-9085-2

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